IEC 60821 : 2.0

VMEBUS - MICROPROCESSOR SYSTEM BUS FOR 1 BYTE TO 4 BYTE DATA

International Electrotechnical Committee

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Foreword
Chapter 0: Introduction
0.1 Scope
0.2 Normative references
0.3 Note to the reader
Chapter 1: Introduction to the IEC 821 BUS standard
1.1 IEC 821 BUS standard objectives
1.2 IEC 821 BUS interface system elements
1.2.1 Basic definitions
1.2.2 Basic IEC 821 BUS structure
1.3 IEC 821 BUS standard diagrams
1.4 Standard terminology
1.4.1 Signal line states
1.4.2 Use of the asterisk (*)
1.5 Protocol specification
1.5.1 Interlocked bus signals
1.5.2 Broadcast bus signal
1.6 System examples and explanations
Chapter 2: IEC 821 BUS data transfer bus
2.1 Introduction
2.2 Data Transfer Bus lines
2.2.1 Addressing lines
2.2.2 Address modifier lines
2.2.3 Data lines
2.2.4 Data Transfer Bus control lines
2.3 DTB modules - Basic description
2.3.1 MASTER
2.3.2 SLAVE
2.3.3 BUS TIMER
2.3.4 LOCATION MONITOR
2.3.5 Addressing modes
2.3.6 Basic data transfer capabilities
2.3.7 Block transfer capabilities
2.3.8 Read-modify-write capabilities
2.3.9 Unaligned transfer capabilities
2.3.10 ADDRESS-ONLY capability
2.3.11 Interaction between DTB functional modules
2.4 Typical operation
2.4.1 Typical data transfer cycles
2.4.2 Address pipelining
2.5 Data Transfer Bus acquisition
2.6 DTB timing rules and observations
Chapter 3: IEC 821 BUS data transfer bus arbitration
3.1 Bus arbitration philosophy
3.1.1 Types of arbitration
3.2 Arbitration bus lines
3.2.1 Bus request and bus grant lines
3.2.2 Bus busy line (BBSY*)
3.2.3 Bus clear line (BCLR*)
3.3 Functional modules
3.3.1 ARBITER
3.3.2 REQUESTER
3.3.3 Data Transfer Bus MASTER
3.4 Typical operation
3.4.1 Arbitration of two different levels of bus request
3.4.2 Arbitration of two bus requests on the same bus
       request line
3.5 Race conditions between MASTER requests and
       ARBITER grants
Chapter 4: IEC 821 BUS Priority interrupt bus
4.1 Introduction
4.1.1 Single handler systems
4.1.2 Distributed systems
4.2 Priority Interrupt Bus lines
4.2.1 Interrupt request lines
4.2.2 Interrupt acknowledge line
4.2.3 Interrupt acknowledge daisy-chain - IACKIN*/IACKOUT*
4.3 Priority Interrupt Bus modules - Basic description
4.3.1 INTERRUPT HANDLERS
4.3.2 INTERRUPTER
4.3.3 IACK DAISY-CHAIN DRIVER
4.3.4 Interrupt handling capabilities
4.3.5 Interrupt request capabilities
4.3.6 STATUS/ID transfer capabilities
4.3.7 Interrupt release capabilities
4.3.8 Interaction between Priority Interrupt Bus modules
4.4 Typical operation
4.4.1 Single handler interrupt operation
4.4.2 Distributed interrupt operation
4.4.3 Example: typical single handler interrupt system
       operation
4.4.4 Example: prioritization of two interrupts in a
       distributed interrupt system
4.5 Race conditions
4.6 Priority Interrupt Bus timing RULES and
       OBSERVATIONS
Chapter 5: IEC 821 BUS Utility Bus
5.1 Introduction
5.2 Utility Bus signal lines
5.3 Utility Bus modules
5.3.1 The SYSTEM CLOCK DRIVER
5.3.2 The SERIAL CLOCK DRIVER
5.3.3 The POWER MONITOR
5.4 System initialization and diagnostics
5.5 Power pins
5.6 RESERVED line
Chapter 6: IEC 821 BUS electrical specifications
6.1 Introduction
6.2 Power distribution
6.2.1 D.C. voltage specifications
6.2.2 Pin and socket connector electrical ratings
6.3 Electrical signal characteristics
6.4 Bus driving and receiving requirements
6.4.1 Bus driver definitions
6.4.2 Driving and loading RULES for all IEC 821 BUS lines
6.5 Backplane signal line interconnections
6.5.1 Termination networks
6.5.2 Characteristic impedance
6.5.3 Additional information
6.6 User defined signals
6.7 Signal line drivers and terminations
Chapter 7: IEC 821 BUS mechanical specifications
7.1 Introduction
7.2 IEC 821 BUS boards
7.2.1 Single height boards
7.2.2 Double height boards
7.2.3 Board connectors
7.2.4 Board assemblies
7.2.5 Board widths
7.2.6 IEC 821 BUS board warpage, lead length and
       component height
7.3 Front panels
7.3.1 Handles
7.3.2 Front panel mounting
7.3.3 Front panel dimensions
7.3.4 Filler panels
7.3.5 Board ejectors/injectors
7.4 Backplanes
7.4.1 Backplane dimensional requirements
7.4.2 Signal line termination networks
7.5 Assembly of IEC 821 BUS subracks
7.5.1 Subracks and slot widths
7.5.2 Subrack dimensions
7.6 IEC 821 BUS backplane connectors and IEC 821 BUS
       board connectors
7.6.1 Pin assignments for the J1/P1 connector
7.6.2 Pin assignments for the J2/J2 connector
Appendix A - Glossary of IEC 821 BUS terms
Appendix B - IEC 821 BUS connector/pin description
Appendix C - Use of the SERCLK and SERDAT* lines
Appendix D - Metastability and resynchronization
Appendix E - Permissible capability subsets
Numerous figures
Numerous tables

Abstract

Defines a high performance backplane bus for use in microprocessor bases systems. This parallel bus supports single- and block-transfer cycles on a 32-bit non-multiplexed address and data highway. Transmission is governed by an asynchronous handshaken protocol. The bus allocation provides for multiprocessor architectures. This bus also supports intermodule interrupts for facilitating quick response to internal and external events.