IEC 61690-2 : 1.0

ELECTRONIC DESIGN INTERCHANGE FORMAT (EDIF) - PART 2: VERSION 400

International Electrotechnical Committee

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Part 1: General introduction
1 Introduction
   1.1 Purposes of an information model for EDIF Version 4 0 0
   1.2 Scope of EDIF Version 4 0 0 (Level 0)
        1.2.1 Categories of design information
        1.2.2 Categories of cell representation
        1.2.3 Organisation of the information model
   1.3 Modelling general concepts
        1.3.1 Containment
        1.3.2 Referencing mechanism
        1.3.3 Instantiation
Part 2: EDIF concepts (Level 0)
2 The structure of an EDIF description
   2.1 Libraries
   2.2 Cells
   2.3 Clusters and view groups
   2.4 Views and symbols
   2.5 Ports and port_bundles
   2.6 Instances
3 Reusable objects
4 Connectivity
   4.1 Logical connectivity
        4.1.1 Signals
        4.1.2 Signal groups
   4.2 Structural connectivity
5 Design hierarchy configuration
6 Design annotation
7 Names
8 Units
9 Geometries
Part 3: Connectivity domain
10 Structural connectivity with wide instances
11 Structural connectivity for connectivity views
   11.1 Connectivity nets and sub-nets
   11.2 Connectivity busses, bus-slices and sub-busses
   11.3 Connectivity rippers
Part 4: Schematic domain
12 Instantiatable templates for schematic domain
13 Structural connectivity for schematic views
   13.1 Schematic pages
   13.2 Schematic nets and sub-nets
   13.3 Schematic busses, bus-slices and sub-busses
Part 5: PCB/MCM domain
14 Materials
15 Bare board technologies
   15.1 Physical layers
   15.2 Drill rules
16 Packages
17 Mountable packages
18 Bare dies and bare die attachment
   18.1 Die bonding technologies
   18.2 Description of dies
   18.3 Die bond pads
   18.4 Mounting of dies
   18.5 Mounting of die bond pads
19 Parts
   19.1 Electrical parts
        19.1.1 Examples of electrical part
   19.2 Connector parts
   19.3 Mechanical parts
   19.4 Jumper parts
   19.5 IBIS information
20 Sub-layouts
   20.1 Layout features
   20.2 Physical nets
21 Embedded dies
22 Figure collectors
   22.1 Example of a simple artwork generation
23 PCB/MCM views
   23.1 Components
   23.2 Component signals
   23.3 Component function allocations
24 Assembled boards
   24.1 Component implementations
   24.2 Component terminal implementations
   24.3 Embedded component implementations
   24.4 Assembled physical nets
   24.5 Jumper connections
25 Technology rules
   25.1 Manufacturing rules
        25.1.1 Physical constraints
        25.1.2 Clearance constraints
   25.2 Assembly rules
   25.3 MCM chips-first technology rules
   25.4 MCM chips-last technology rules
26 Drawings
   26.1 Drawing borders
   26.2 Drawing title blocks
   26.3 Annotation
   26.4 Board subset placements
   26.5 Dimensioning
        26.5.1 Linear dimensioning
        26.5.2 Circular dimensioning
        26.5.3 Angular dimensioning
        26.5.4 Positioning of dimensioning
        26.5.5 Dimensioning attributes
27 Instantiatable templates for PCB/MCM domain
References
Figures
Tables

Abstract

Gives a general overview of the information model, it gives a description of the techniques used for modelling various EDIF concepts. Also defines the functions of an information model for EDIF. It includes a general discussion of major topics in EDIF.