IEC 60822 : 1.0

Abstract

The VSB bus was designed to meet the needs of multiprocessor systems based on high performance 32 bit microprocessors built up from board assemblies. It includes a high speed asynchronous data transfer bus allowing masters to direct the transfer of binary data to and from slaves according to 4 kinds of cycles: address only, single transfer, block transfer, and interrupt acknowledge cycles. It also includes an arbitration bus enabling arbiter modules and/or requester modules to coordinate the use of the data transfer bus according to two arbitration methods (series or parallel).

General Product Information

Published
Document Type	Standard
Status	Current
Publisher	International Electrotechnical Committee
Pages
ISBN
Committee	JTC1/SC 26