DELAY AND POWER CALCULATION STANDARDS - PART 3: STANDARD DELAY FORMAT (SDF) FOR THE ELECTRONIC DESIGN PROCESS
International Electrotechnical Committee
FOREWORD
IEEE Introduction
1 Overview
1.1 Scope
1.2 Organization of this standard
2 References
3 Conventions
3.1 Terminology conventions
3.2 Syntactic conventions
4 SDF in the design process
4.1 Sharing of timing data
4.2 Using multiple SDF files in one design
4.3 Timing data and constraints
4.4 Timing environments
4.5 Back-annotation of timing data for design analysis
4.6 Forward-annotation of timing constraints for design
synthesis
4.7 Timing models supported by SDF
5 Defining the standard delay format
5.1 SDF file content
5.2 Header section
5.3 Cells
5.4 Delays
5.5 Timing checks
5.6 Labels
5.7 Timing environment
Annex A (normative) Syntax of SDF
Annex B (informative) SDF file examples
Annex C (informative) List of Participants
Describes Standard Delay Format (SDF) an existing OVI standard for the representation and interpretation of timing data for use at any stage of the electronic design process. It serve as a complete specification of the Standard Delay Format (SDF). It contains: - Detailed information on how SDF is used in the design process. - Detailed semantic descriptions of all SDF constructs. - The formal syntax. - Examples.
| Document Type | Standard |
| Status | Current |
| Publisher | International Electrotechnical Committee |
| Committee | TC 93 |
