IEC 61691-6 : 1.0
IEC 61691-6 : 1.0
BEHAVIOURAL LANGUAGES - PART 6: VHDL ANALOG AND MIXED-SIGNAL EXTENSIONS
International Electrotechnical Committee
BEHAVIOURAL LANGUAGES - PART 6: VHDL ANALOG AND MIXED-SIGNAL EXTENSIONS
International Electrotechnical Committee
Foreword
IEEE introduction
0 Overview
1 Design entities and configurations
2 Subprograms and packages
3 Types and natures
4 Declarations
5 Specifications
6 Names
7 Expressions
8 Sequential statements
9 Concurrent statements
10 Scope and visibility
11 Design units and their analysis
12 Elaboration and execution
13 Lexical elements
14 Predefined language environment
15 Simultaneous statements
Annex A (informative) - Syntax summary
Annex B (informative) - Glossary
Annex C (informative) - Potentially nonportable constructs
Annex D (informative) - Changes from IEEE Std 1076.1-1999
Annex E (informative) - Features under consideration for
removal
Annex F (informative) - Bibliography
Annex G (informative) - List of Participants
Index
Provides a hardware description language for the description and the simulation of analog, digital, and mixed-signal systems.
Document Type | Standard |
Status | Current |
Publisher | International Electrotechnical Committee |
Committee | TC 93 |