IEEE 1014 : 1987

VERSATILE BACKPLANE BUS (VME BUS), STANDARD FOR A

Institute of Electrical & Electronics Engineers

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1 Introduction
1.1 Objectives
1.2 Interface system elements
1.2.1 Basic definitions
1.2.1.1 Terms used to describe the mechanical structure
1.2.1.2 Terms used to describe the functional structure
1.2.1.3 Types of cycles
1.2.2 Basic structure
1.2.2.1 Data transfer bus
1.2.2.2 DTB arbitration bus
1.2.2.3 Priority interrupt bus
1.2.2.4 Utility bus
1.3 Specification diagrams
1.4 Terminology
1.4.1 Signal line state
1.4.2 Use of the asterisk
1.5 Protocol
1.5.1 Interlocked bus signal
1.5.2 Broadcast bus signal
1.6 System examples and explanations
2 Data transfer bus
2.1 Introduction
2.2 Data-transfer-bus lines
2.2.1 Addressing lines
2.2.2 Address-modifier lines
2.2.3 Data lines
2.2.4 Data-transfer-bus control lines
2.2.4.1 AS*
2.2.4.2 DS0* and DS1*
2.2.4.3 DTACK*
2.2.4.4 BERR*
2.2.4.5 WRITE*
2.3 DTB modules - basic description
2.3.1 Master
2.3.2 Slave
2.3.3 Bus timer
2.3.4 Location monitor
2.3.5 Addressing modes
2.3.6 Basic data transfer capabilities
2.3.7 Block-transfer capabilities
2.3.8 Read-modify-write capabilities
2.3.9 Unaligned transfer capability
2.3.10 Address-only capability
2.3.11 Interaction between DTB functional modules
2.4 Typical operation
2.4.1 Typical data-transfer cycles
2.4.2 Address pipelining
2.5 Data-transfer-bus acquisition
2.6 DTB timing rules and observations
3 DTB arbitration bus
3.1 Introduction
3.2 Arbitration bus lines
3.2.1 Bus request and bus grant lines
3.2.2 Bus busy line (BBSY*)
3.2.3 Bus clear line (BCLR*)
3.3 Functional modules
3.3.1 Arbiter
3.3.2 Requester
3.3.3 Data-transfer-bus master
3.3.3.1 Release of the DTB
3.3.3.2 Acquisition of the DTB
3.3.3.3 Other information
3.4 Typical operation
3.4.1 Arbitration of two different levels of bus
         request
3.4.2 Arbitration of two bus requests on the same bus
         request line
3.5 Race conditions between master requests and
         arbiter grants
4 Priority interrupt bus
4.1 Introduction
4.1.1 Single handler systems
4.1.2 Distributed systems
4.2 Priority interrupt bus lines
4.2.1 Interrupt request lines
4.2.2 Interrupt acknowledge line
4.2.3 Interrupt acknowledge daisy-chain
4.3 Priority interrupt bus modules - basic
         description
4.3.1 Interrupt handlers
4.3.2 Interrupters
4.3.3 IACK daisy-chain driver
4.3.4 Interrupt handling capabilities
4.3.5 Interrupt request capabilities
4.3.6 Status/ID transfer capabilities
4.3.7 Interrupt release capabilities
4.3.8 Interaction between priority interrupt bus
         modules
4.4 Typical operation
4.4.1 Single handler interrupt operation
4.4.2 Distributed interrupt operation
4.4.2.1 Distributed interrupt systems with seven
         interrupt handlers
4.4.2.2 Distributed interrupt systems with two to six
         interrupt handlers
4.4.3 Example: typical single handler interrupt
         system operation
4.4.4 Example: prioritization of two interrupts in a
         distributed interrupt system
4.5 Race conditions
4.6 Priority interrupt bus timing rules and
         observations
5 Utility bus
5.1 Introduction
5.2 Utility bus signal lines
5.3 Utility bus modules
5.3.1 The system clock driver
5.3.2 The serial clock driver
5.3.3 The power monitor
5.4 System initialization and diagnostics
5.5 Power pins
5.6 Reserved line
6 Electrical specifications
6.1 Introduction
6.2 Power distribution
6.2.1 DC voltage specifications
6.2.2 Pin and socket connector electrical ratings
6.3 Electrical signal characteristics
6.4 Bus driving and receiving requirements
6.4.1 Bus driver definitions
6.4.2 Driving and loading rules for all lines
6.4.2.1 Driving and loading rules for high-current
         three-state lines (AS*, DS0*, DS1*)
6.4.2.2 Driving and loading rules for standard three-
         state lines (A01-A31, D00-D31, AM0-AM5, IACK*,
         LWORD*, WRITE*)
6.4.2.3 Driving and loading rules for high-current
         totem-pole lines (SERCLK, SYSCLK, BCLR*)
6.4.2.4 Driving and loading rules for standard totem-
         pole lines (BG0OUT*-BG3OUT*/BG0IN*-BG3IN*,
         IACKOUT*/IACKIN)
6.4.2.5 Driving and loading rules for open-collector
         lines (BR0*-BR3*, BBSY*, IRRQ1*-IRQ7*, DTACK*,
         BERR*, SYSFAIL*, SYSRESET*, ACFAIL*, and IACK*)
6.5 Backplane signal line interconnections
6.5.1 Termination networks
6.5.2 Characteristic impedance
6.5.3 Additional information
6.6 User-defined signals
6.7 Signal line drivers and terminations
7 Mechanical specifications
7.1 Introduction
7.2 Boards
7.2.1 Single-height boards
7.2.2 Double-height boards
7.2.3 Board connectors
7.2.4 Board assemblies
7.2.5 Board widths
7.2.6 Board warpage, lead length, and component
         height
7.3 Front panels
7.3.1 Handles
7.3.2 Front panel mounting
7.3.3 Front panel dimensions
7.3.4 Filler panels
7.3.5 Board ejectors and injectors
7.4 Backplanes
7.4.1 Backplane dimensional requirements
7.4.2 Signal line termination networks
7.5 Assembly of subracks
7.5.1 Subracks and slot widths
7.5.2 Subrack dimensions
7.6 Backplane connectors and board connectors
7.6.1 Pin assignments for the J1/P1 connector
7.6.2 Pin assignments for the J2/P2 connectors
NUMEROUS FIGURES
NUMEROUS TABLES
Appendixes
Appendix A Glossary
Appendix B Signal line description
Appendix C Use of the SERCLK and SERDAT* lines
Appendix D Metastability and synchronization
Appendix E Permissible capability subsets
Appendix Figures
Appendix Tables

Abstract

Describes an interfacing system used to interconnect data storage, data processing and peripheral control devices in a tightly coupled hardware configuration.