IEEE 1076.3 : 1997
IEEE 1076.3 : 1997
VHDL SYNTHESIS PACKAGES
Institute of Electrical & Electronics Engineers
VHDL SYNTHESIS PACKAGES
Institute of Electrical & Electronics Engineers
1 Overview
1.1 Scope
1.2 Terminology
1.3 Conventions
2 References
3 Definitions
4 Interpretation of the standard logic types
4.1 The STD_LOGIC_1164 values
4.2 Static constant values
4.3 Interpretation of logic values
5 The STD_MATCH function
6 Signal edge detection
7 Standard arithmetic packages
7.1 Allowable modifications
7.2 Compatibility with IEEE Std 1076-1987
7.3 The package texts
Annex A (informative) Notes on the package functions
A.1 General considerations
A.2 Arithmetic operator functions
A.3 Relational operator functions
A.4 Shift functions
A.5 Type conversion functions
A.6 Logical operator functions
A.7 The STD_MATCH function
Document Type | Standard |
Status | Current |
Publisher | Institute of Electrical & Electronics Engineers |
Supersedes |
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