IEEE 1581 : 2011

Table of Contents

1. Overview
2. Normative references
3. Definitions, acronyms, and abbreviations
4. Test architecture
5. Classification of device pins
6. Test mode behavior
7. Test mode control
8. Test logic
9. Conformance and documentation
Annex A (informative) - Bibliography

Abstract

Specifies a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1[TM]) is not feasible.

General Product Information

Published
Document Type	Standard
Status	Current
Publisher	Institute of Electrical & Electronics Engineers
Pages
ISBN